CS4953XX_08 Datasheet, PDF (1/34 Pages) Cirrus Logic – 32-bit Audio Decoder DSP Family

CS4953xx Data Sheet
FEATURES
32-bit Audio Decoder DSP Family
‰ Multi-standard 32-bit Audio Decoding plus Post
with Dual DSP Engine Technology
Processing
‰ Framework^™ Applications Library in ROM
— Dolby Digital^® EX, Dolby^® Pro Logic^® IIx, Dolby
‰ Large On-chip X, Y, and Program RAM & ROM
‰ SDRAM and Serial Flash Memory Support
Headphone^®, Dolby^® Virtual Speaker^®
The CS4953xx DSP family are the enhanced versions of the
— DTS-ES 96/24^™, DTS-ES^™ Discrete 6.1, DTS-ES^™
CS495xx DSP family with higher overall performance and
Matrix 6.1, DTS:Neo6^™
— AAC^™ Multichannel 5.1
lower system cost. The CS4953xx includes all mainstream
audio processing codes in on-chip ROM. This saves external
memory for code storage. In addition, the intensive decoding
— SRS^® CS2^® and TSXT^®
tasks of Dolby Digital^® Surround EX^®, AAC multi-channel,
— THX^® Ultra2^™, THX^® ReEQ^™
— Cirrus Original Multi-Channel Surround (COMS)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processor including: 7.1Bass
Manager, Tone Control, 12- Band Parametric EQ,
Y Delay, 1:2 Upsampler
— Microsoft^® HDCD^®
‰ Framework^™ Applications for Download
R _{— Thomson MP3 Surround}
— Internal DSD-to-PCM Conversion
‰ Up to 12 Channels of 32-bit Serial Audio Input
A _{‰ 6 Channel DSD Input}
‰ 16 Ch x 32-bit PCM Out with either two 192 kHz S/PDIF
Tx (144-pin package) or one 192 kHz S/PDIF Tx (128-pin
IN ^package)
‰ Two SPI^™/I²C^®, one Parallel and one UART Port
‰ Customer Software Security Keys
DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone
can be accomplished without the expense of external
SDRAM memory.
With larger internal memories than the CS495xx, the
CS49531x is designed to support up to 150 ms per channel
of lip-sync delay. With 150 MHz internal clock speed, the
CS4953xx supports the most demanding post-processing
requirements. It is also designed for easy upgrading.
Customers currently using the CS495xx can upgrade to the
CS4953xx with minor hardware and software changes.
Ordering Information
See page 28 for ordering information.
IM _Serial
Control 1
L _{12 Ch. Audio In /}
6 Ch. SACD In
E _{S/PDIF S/PDIF}
R_{16 Ch PCM}
P^{Audio Out}
Serial
Control 2
Parallel
Control
UART
GPIO
32-bit
DSP A
D
M
A
32-bit
DSP B
PXY
PXY
Debug
STC
TMR1
TMR2
Ext. Memory Controller
PLL
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright 2008 Cirrus Logic,
SEP ’08
DS705PP3