CL-PS7111 Datasheet, PDF (1/105 Pages) Cirrus Logic – Low-Power System-on-a-Chip

CL-PS7111
Preliminary Data Book
FEATURES
s Ultra low power
— Designed for applications that require long battery life
while using standard AA/AAA batteries
— Average 45 mW/66 mW in normal operation (2.7 V/3.3 V,
13 MHz/18.432 MHz)
— Average 15 mW in idle mode (clock to the CPU stopped,
everything else running)
— Average 15 µA in standby mode (realtime clock on,
everything else stopped)
s Performance matching 33-MHz Intel^®
’486-based PC
— 15 Vax™-MIPS (Dhrystone^®) at 18 MHz
s ARM710a microprocessor
— ARM7 CPU
— 8 Kbytes of four-way set-associative cache
— MMU with 64-entry TLB (transition look-aside buffer)
s DRAM controller
— Supports both 16- and 32-bit-wide DRAMs
s ROM/SRAM/flash memory control
— Decodes 4, 5, or 6 separate memory segments of 256
Mbytes
(cont.)
Low-Power System-on-a-Chip
OVERVIEW
The CL-PS7111 is designed for ultra-low-power
applications such as organizers/PDAs, two-way
pagers, smart phones, and hand-held internet appli-
ances. The core-logic functionality of the device is
built around an ARM710a microprocessor with 8
Kbytes of four-way set-associative unified cache.
At 18.432 MHz (for 3.3-V operation), the
CL-PS7111 delivers nearly 15 Vax-MIPS of perfor-
mance (based on Dhrystone^® benchmark) —
roughly the same level of performance offered by
a 33-MHz Intel^® ’486-based PC.
(cont.)
Functional Block Diagram
13-MHz INPUT
3.6864 MHz
32.768 kHz
EINT[1–3], FIQ,
MEDCHG
BATOK, EXTPWR
PWRFL, BATCHG
PORTS A, B, D (8-BIT)
PORT E (3-BIT)
KEYBOARD COLUMN
DRIVERS (0–7)
BUZZER DRIVE
DC TO DC
18.432-MHz
PLL
32.768-kHz
OSCILLATOR
INTERRUPT
CONTROLLER
POWER
MANAGEMENT
GPIO
PSU
CONTROL
ARM710a
ARM7
µP CORE
8-KBYTE
CACHE
MMU
COUNTERS
(2)
INTERNAL DATA BUS
STATE
CONTROL
CL-PS6700
INTFC.
ROM/EXPANSION
CONTROL
DRAM
CONTROLLER
INTERNAL
ADDRESS BUS
MUX
D0–D31
POR, RUN,
RESET, WAKEUP
PB[0–1], CS[4–5]
EXPCLK, WORD,
CD[0–3], EXPRDY,
WRITE
MOE, MWE
RAS[0–1], CAS[0–3]
A[0–27],
DRA[0–12]
LCD
CONTROLLER
LCD DRIVE
ADCCLK, ADCIN,
ADCOUT, SMPCLK,
RXFS, TXFS
PCMCLK, PCMSYNC
PCMIN, PCMOUT
SYNC. SERIAL
INTERFACE
CODEC INTFC.
RTC
ON-CHIP
BOOT ROM
SRAM
2 KBYTE
UART
UART
IRDA
LED AND
PHOTODIODE
ASYNC INTERFACE 1
ASYNC INTERFACE 2
Version 2.0
September 1997