CL-PS7110 Datasheet, PDF (1/82 Pages) Cirrus Logic – Low-Power System-on-a-Chip

CL-PS7110
Data Book
FEATURES
s Ultra low power
— Designed for applications that require long battery life
while using standard AA/AAA batteries
— Average 20 mA in normal operation (everything on)
— Average 5 mA in idle mode (clock to the CPU stopped,
everything else running)
— Average 3 µA in standby mode (realtime clock on and
everything else stopped)
s Performance matching 33-MHz Intel^® ’486-based
PC
— 15 Vax™-MIPS (Dhrystone^®) at 18 MHz
s ARM710A microprocessor
— ARM7 CPU
— 8 Kbytes of four-way set-associative cache
— MMU with 64-entry TLB (transition look-aside buffer)
— Little endian
s DRAM controller
— Connects up to four banks of DRAM, with each bank
being 32 bits wide and up to 256 Mbytes in size
(cont.)
Functional Block Diagram
Low-Power
System-on-a-Chip
OVERVIEW
The CL-PS7110 is designed for ultra-low-power
applications such as organizers/PDAs, two-way
pagers, smart phones, and hand-held internet
browsers. The device’s core-logic functionality is
built around an ARM710A microprocessor with 8
Kbytes of four-way set-associative unified cache.
At 18.432 MHz (for 3-V operation), the CL-PS7110
delivers nearly 15 Vax-MIPS of performance (based
on Dhrystone^® benchmark) — roughly the same
(cont.)
3.6864 MHz
32.786 kHz
EINT[1–3],
FIQ
BATOK, EXTPWR
PWRFL, BATCHG
PORTS A B C D — 8-BIT
PORT E — 4-BIT
KEYBOARD COLUMN
DRIVES (0–7)
BUZZER DRIVE
DC TO DC
CLK, SYNC, IN,
OUT, SMPCLK
CLK, SYNC IN,
OUT
18.432-MHz
PLL
32.768-kHz
OSCILLATOR
INTERRUPT
CONTROLLER
POWER
MANAGEMENT
GPIO
PSU
CONTROL
SYNCHRONOUS
SERIAL I/O
CODEC
INTERFACE
ARM710A
ARM7
µP CORE
8-KBYTE
CACHE
MMU
COUNTERS
(2)
RTC
INTERNAL DATA BUS
STATE
CONTROL
ROM/EXPANSION
CONTROL
DRAM
CONTROLLER
INTERNAL
ADDRESS BUS
MUX
D0–D31
POR, RUN,
RESET,
WAKEUP
EXPCLK, WORD,
CD[0–7], EXPRDY,
WRITE
MOE, MWE
RAS[0–3], CAS[0–3]
A[0–27],
DRA[0–12]
LCD
CONTROLLER
LCD DRIVE
UART
IRDA
LED AND PHOTO-
DIODE
RS232 INTERFACE
Version 1.5
May 1997