CS5132 Datasheet, PDF (11/19 Pages) Cherry Semiconductor Corporation – Dual Output CPU Buck Controller

Application Information: continued
CS5132-based Dual Output
Buck Regulator Design Example
Step 1: Define Specification
Input Voltage from Òsilver boxÓ power supply
¥ 5V ±5% for conversion to output voltage
¥ 12V ±5% for NFET Gate Voltage and circuit bias
Output Voltages
Â¥ 2.0V @ 16A for V_CC(CORE)
Â¥ 3.3V@ 8A for V_I/O
Â¥ 5% Overall Voltage accuracy (load, line, temperature,
ripple)
Â¥ 2% DC & 5% AC Voltage Accuracy
Â¥ < 2% Output Ripple Voltage
¥ 15A Load Step @ 20A /µs - V_CC(CORE)
¥ 7A Load Step @ 5A/µs - V_I/O
Thermal Management
¥ 0 to 50û C ambient temperature range
Â¥ Component junction temperatures within manufactur-
erÕs specified ratings at full load & T_A(MAX)
Components
Â¥ Low cost is top priority.
Â¥ Surface mount when possible
Â¥ Small footprint important
Â¥ Component Ratings determined at 80% of Maximum
Load
Step 2: Determine Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the regulator output voltage. Key
specifications for input capacitors are their ripple rating,
while ESR is important for output capacitors. For best tran-
sient response, a combination of low value/high frequency
and bulk capacitors placed close to the load will be
required.
Step 2a: For the 2V Output (V_CC(CORE))
The load transients have slew rates of up to 20A /µs, while
the voltage drop during a transient must be kept to less
than 100mV. The output capacitors must hold the output
voltage within these limits since the inductor current can
not change with the required slew rate. The output capaci-
tors must therefore have a very low ESL and ESR.
The voltage transient during the load step is
( ) ^{DVOUT = DIOUT ´}
ESL
t_TR
Dt ^{+ ESR + C}OUT ^,
where t_TR = output voltage transient response time.
The total change in output voltage is divided as follows:
ESR - 80mV
ESL - 10mV
Output Capacitor Discharge During Transient - 10mV
Maximum allowable ESR is:
0.08V
ESR = _15A = 5.3m½.
The ESR for a 1200µF/10V Sanyo capacitor type GX is
44m½ per capacitor.
Number of Capacitors =
44
5.3
@ 8.
44
Total ESR = ₈ = 5.5m½.
Output voltage deviation due to ESR:
DV = 15A ´ 5.5m½ = 82mV.
The ESL is calculated from
DI
Dt
=
20A
µs
,
ESL = ^{DV ´ Dt} = ^{0.01V ´ 1 ´ 10-6} = 0.5nH.
DI
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It is estimated that a 10 ´ 12 mm Aluminum Electrolytic
capacitor has approximately 4nH of package inductance. In
this case we have eight (8) capacitors in parallel for a total
capacitor ESL:
ESL = ^4nH = 0.5nH.
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Output voltage deviation due to ESL:
DV = ^{ESL ´ DI} = ^{0.5nH ´ 20A} = 10mV.
Dt
1µs
The change in capacitor voltage during the transient is:
DV_C =
DI ´ t_{TR ,}
C_OUT
where t_TR is the output voltage transient response time. We
choose t_TR = 6µs:
DV_C =
15A ´ 6µs
8 ´ 1200µF
= 9mV.
Total change in output voltage as a result of an increase in
load current of a 15A step with a 20A/µs slew rate is:
DV_OUT = ( 82mV + 10mV + 9mV ) = 101mV.
Step 2b: For the 3.3V Output (V_I/O)
The V_I/O load transients have slew rates of 5A/µs, while
the voltage drop during a transient must be kept to less
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