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CEP4060AL_10 Datasheet, PDF (4/4 Pages) Chino-Excel Technology – N-Channel Enhancement Mode Field Effect Transistor
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CEP4060AL/CEB4060AL
15 VDS=48V
ID=15A
12
9
6
RDS(ON)Limit
101
10ms
100µs
1ms
10ms
DC
3
0
0
4
8
12
16
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
VDD
RL
VIN
D
VOUT
VGS
RGEN G
S
100
TC=25 C
TJ=175 C
Single Pulse
100
101
102
VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
100
D=0.5
0.2
10-1
0.1
0.05
0.02
0.01
Single Pulse
10-2
10-2
10-1
100
101
102
Square Wave Pulse Duration (msec)
PDM
t1
t2
1. R JA (t)=r (t) * R JA
2. R JA=See Datasheet
3. TJM-TA = P* R JA (t)
4. Duty Cycle, D=t1/t2
103
104
Figure 11. Normalized Thermal Transient Impedance Curve
4