CEP13N5 Datasheet, PDF (4/4 Pages) Chino-Excel Technology – N-Channel Enhancement Mode Field Effect Transistor

CEP13N5/CEB13N5
CEF13N5
10 _VDS=400V
I_D=13A
8
6
4
2
0
0
15
30
45
60
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
VDD
RL
VIN
D
VOUT
VGS
RGEN _G
S
10² R_DS(ON)Limit
100ms
10¹
1ms
10ms
DC
10⁰
T_C=25 C
T_J=175 C
10^{-1 Single Pulse}
10⁰
10¹
10²
10³
VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
10⁰
D=0.5
0.2
10^-1
0.1
0.05
0.02
0.01
Single Pulse
10^-2
10^-5
10^-4
10^-3
10^-2
10^-1
Square Wave Pulse Duration (msec)
PDM
t1
t2
1. R JC (t)=r (t) * R JC
2. R JC=See Datasheet
3. TJM-TC = P* R JC (t)
4. Duty Cycle, D=t1/t2
10⁰
10¹
Figure 11. Normalized Thermal Transient Impedance Curve
4