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CED63A3 Datasheet, PDF (4/4 Pages) Chino-Excel Technology – N-Channel Enhancement Mode Field Effect Transistor
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CED63A3/CEU63A3
10 VDS=15V
ID=45A
8
6
4
2
0
0
9
18
27
36
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
VDD
RL
VIN
D
VOUT
VGS
RGEN G
S
103
RDS(ON)Limit
102
100ms
1ms
10ms
101
DC
TC=25 C
TJ=150 C
100 Single Pulse
10-1
100
101
6
102
VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
100
D=0.5
0.2
10-1
0.1
0.05
0.02
0.01
Single Pulse
10-2
10-5
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (msec)
PDM
t1
t2
1. R JC (t)=r (t) * R JC
2. R JC =See Datasheet
3. TJM-TC = P* R JC (t)
4. Duty Cycle, D=t1/t2
100
101
Figure 11. Normalized Thermal Transient Impedance Curve
4