CEP62A3 Datasheet, PDF (1/5 Pages) Chino-Excel Technology – N-Channel Logic Level Enhancement Mode Field Effect Transistor

CEP62A3/CEB62A3
Feb. 2003
N-Channel Logic Level Enhancement Mode Field Effect Transistor ₄₄
FEATURES
30V , 60A , RDS(ON)=10mΩ @VGS=10V.
D
RDS(ON)=15mΩ @VGS=4.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-220 & TO-263 package.
G
D
G
G
S
D
S
S
CEB SERIES
CEP SERIES
TO-263(DD-PAK)
TO-220
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous
ID
-Pulsed
IDM
Drain-Source Diode Forward Current
IS
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
PD
TJ, TSTG
Limit
30
Ć20
60
180
60
68
0.45
-55 to 175
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
RįJC
2.2
C/W
Thermal Resistance, Junction-to-Ambient
RįJA
62.5
C/W
4-177