CEG8304 Datasheet, PDF (1/4 Pages) Chino-Excel Technology – Dual P-Channel Enhancement Mode Field Effect Transistor

CEG8304
Dual P-Channel Enhancement Mode Field Effect Transistor
PRELIMINARY
FEATURES
-30V, -3.6A, R_DS(ON) = 58mΩ @V_GS = -10V.
R_DS(ON) = 85mΩ @V_GS = -4.5V.
Super High dense cell design for extremely low RDS(ON).
High power and current handing capability.
Lead free product is acquired.
TSSOP-8 for Surface Mount Package.
D1 1
S1 2
S1 3
G1 4
G2
S2
S2
D
TSSOP-8
G1
S1
S1
D
8 D2
7 S2
6 S2
5 G2
ABSOLUTE MAXIMUM RATINGS T_A = 25 C unless otherwise noted
Parameter
Symbol
Limit
Drain-Source Voltage
Gate-Source Voltage
V_DS
-30
V_GS
±20
Drain Current-Continuous
Drain Current-Pulsed ^a
I_D
-3.6
I_DM
-14
Maximum Power Dissipation
P_D
1.25
Operating and Store Temperature Range
TJ,Tstg
-55 to 150
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Ambient ^b
Symbol
RθJA
Limit
100
Units
V
V
A
A
W
C
Units
C/W
This is preliminary information on a new product in development now .
Details are subject to change without notice .
1
Rev 1. 2008.June
http://www.cetsemi.com