CEF08N5 Datasheet, PDF (1/5 Pages) Chino-Excel Technology – N-Channel Logic Level Enhancement Mode Field Effect Transistor

CEF08N5
PRELIMINARY
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
500V , 4.7A , RDS(ON)=0.85Ω @VGS=10V.
D
6
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-220F full-pak for through hole
G
G
D
S
S
TO-220F
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous
ID
-Pulsed
IDM
Drain-Source Diode Forward Current
IS
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperautre Range
PD
TJ, TSTG
Limit
500
Ć30
4.7
15
4.7
48
0.38
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
RįJC
2.6
C/W
Thermal Resistance, Junction-to-Ambient
RįJA
65
C/W
6-142