CED9926 Datasheet, PDF (1/5 Pages) Chino-Excel Technology – N-Channel Logic Level Enhancement Mode Field Effect Transistor

CED9926/CEU9926
PRELIMINARY
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
20V , 26A , RDS(ON)=30mΩ @VGS=4.5V.
D
6
RDS(ON)=40mΩ @VGS=2.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-251 & TO-252 package.
G
D
G
S
G
DS
CEU SERIES
TO-252AA(D-PAK)
CED SERIES
TO-251(l-PAK)
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous
ID
-Pulsed
IDM
Drain-Source Diode Forward Current
IS
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
PD
TJ, TSTG
Limit
20
Ć12
26
78
26
38
0.25
-55 to 175
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
RįJC
4
C/W
Thermal Resistance, Junction-to-Ambient
RįJA
50
C/W
6-82