CED41A2 Datasheet, PDF (1/4 Pages) Chino-Excel Technology – N-Channel Enhancement Mode Field Effect Transistor

CED41A2/CEU41A2
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
20V, 36A, R_DS(ON) = 20mΩ @V_GS = 4.5V.
R_DS(ON) = 30mΩ @V_GS = 2.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handing capability.
D
Lead free product is acquired.
TO-251 & TO-252 package.
D
G
G
S
G
DS
CEU SERIES
TO-252(D-PAK)
CED SERIES
TO-251(I-PAK)
S
ABSOLUTE MAXIMUM RATINGS Tc = 25 C unless otherwise noted
Parameter
Symbol
Limit
Drain-Source Voltage
V_DS
Gate-Source Voltage
V_GS
Drain Current-Continuous
I_D
Drain Current-Pulsed ^a
I_DM
Maximum Power Dissipation @ T_C = 25 C
- Derate above 25 C
P_D
20
±12
36
100
43
0.29
Operating and Store Temperature Range
TJ,Tstg
-55 to 175
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
RθJC
RθJA
Limit
3.5
50
Units
V
V
A
A
W
W/ C
C
Units
C/W
C/W
Rev 1. 2005.May
6 - 62
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