CMLDM8005_13 Datasheet, PDF (2/3 Pages) Central Semiconductor Corp – SURFACE MOUNT SILICON DUAL P-CHANNEL ENHANCEMENT-MODE MOSFET

CMLDM8005
SURFACE MOUNT SILICON
DUAL P-CHANNEL
ENHANCEMENT-MODE
MOSFET
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted)
SYMBOL TEST CONDITIONS
MIN
TYP
UNITS
gFS
VDS=10V, ID=200mA
0.2
S
Crss
VDS=16V, VGS=0, f=1.0MHz
25
pF
Ciss
VDS=16V, VGS=0, f=1.0MHz
100
pF
Coss
VDS=16V, VGS=0, f=1.0MHz
21
pF
Qg(tot) VDS=10V, VGS=4.5V, ID=200mA
1.2
nC
Qgs
VDS=10V, VGS=4.5V, ID=200mA
0.24
nC
Qgd
VDS=10V, VGS=4.5V, ID=200mA
0.36
nC
ton
VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω
38
ns
toff
VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω
48
ns
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATION
w w w. c e n t r a l s e m i . c o m
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODE: CC8
R4 (5-June 2013)