CMLDM7585_13 Datasheet, PDF (2/4 Pages) Central Semiconductor Corp – SURFACE MOUNT SILICON N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY MOSFETS

CMLDM7585
SURFACE MOUNT SILICON
N-CHANNEL AND P-CHANNEL
ENHANCEMENT-MODE
COMPLEMENTARY MOSFETS
ELECTRICAL CHARACTERISTICS - Continued: (TA=25°C)
SYMBOL TEST CONDITIONS
gFS
VDS=10V, ID=400mA
gFS
VDS=10V, ID=200mA
Crss
VDS=16V, VGS=0, f=1.0MHz
Ciss
VDS=16V, VGS=0, f=1.0MHz
Coss
VDS=16V, VGS=0, f=1.0MHz
Qg(tot)
VDS=10V, VGS=4.5V, ID=500mA
Qg(tot)
VDS=10V, VGS=4.5V, ID=200mA
Qgs
VDS=10V, VGS=4.5V, ID=500mA
Qgs
VDS=10V, VGS=4.5V, ID=200mA
Qgd
VDS=10V, VGS=4.5V, ID=500mA
Qgd
VDS=10V, VGS=4.5V, ID=200mA
ton
VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω
toff
VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω
N-CH (Q1)
MIN TYP
1.0
-
-
-
-
18
-
100
-
16
-
1.58
-
-
-
0.17
-
-
-
0.24
-
-
-
10
-
25
SOT-563 CASE - MECHANICAL OUTLINE
P-CH (Q2)
MIN TYP
-
-
0.2
-
-
25
-
100
-
21
-
-
-
1.2
-
-
-
0.24
-
-
-
0.36
-
38
-
48
UNITS
S
S
pF
pF
pF
nC
nC
nC
nC
nC
nC
ns
ns
PIN CONFIGURATION
w w w. c e n t r a l s e m i . c o m
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODE: 87C
R4 (5-June 2013)