CMLDM7003E_15 Datasheet, PDF (2/4 Pages) Central Semiconductor Corp – SURFACE MOUNT SILICON DUAL N-CHANNEL

CMLDM7003E
CMLDM7003JE
ENHANCED SPECIFICATION
SURFACE MOUNT SILICON
DUAL N-CHANNEL
ENHANCEMENT-MODE
MOSFETS
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted)
SYMBOL TEST CONDITIONS
TYP
MAX
UNITS
Qg(tot)
VDS=25V, VGS=4.5V, ID=100mA
0.764
nC
Qgs
VDS=25V, VGS=4.5V, ID=100mA
0.148
nC
Qgd
VDS=25V, VGS=4.5V, ID=100mA
0.156
nC
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATIONS
CMLDM7003E (USA Pinout)
CMLDM7003JE (Japanese Pinout)
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
MARKING CODE: C73
w w w. c e n t r a l s e m i . c o m
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODE: C7J
R5 (8-June 2015)