CMLDM7002A_10 Datasheet, PDF (2/2 Pages) Central Semiconductor Corp – SURFACE MOUNT DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET

CMLDM7002A
CMLDM7002AG*
CMLDM7002AJ
SURFACE MOUNT
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted)
SYMBOL TEST CONDITIONS
MIN
MAX
UNITS
Crss
Ciss
Coss
VDS=25V, VGS=0, f=1.0MHz
VDS=25V, VGS=0, f=1.0MHz
VDS=25V, VGS=0, f=1.0MHz
5.0
pF
50
pF
25
pF
ton / toff
VDD=30V, VGS=10V, ID=200mA
RG=25Ω, RL=150Ω
20
ns
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATIONS
CMLDM7002A (USA Pinout)
CMLDM7002AG*
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
CMLDM7002AJ (Japanese Pinout)
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODES:
CMLDM7002A: L02
CMLDM7002AG*: C2G
* Device is Halogen Free by design
w w w. c e n t r a l s e m i . c o m
MARKING CODE: 02J
R5 (18-January 2010)