CTLDM8120-M621H Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – SURFACE MOUNT P-CHANNEL ENHANCEMENT-MODE SILICON MOSFET

CTLDM8120-M621H
SURFACE MOUNT
P-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
w w w. c e n t r a l s e m i . c o m
DESCRIPTION:
The CENTRAL SEMICONDUCTOR
CTLDM8120-M621H is a very low profile (0.4mm)
P-Channel enhancement-mode MOSFET in a small,
thermally efficient, 1.5mm x 2mm TLM™ package.
MARKING CODE: CNF
TLM621H CASE
• Device is Halogen Free by design
APPLICATIONS:
• Load / Power Switches
• Power Supply Converter Circuits
• Battery Powered Portable Equipment
FEATURES:
• Low rDS(ON) (0.24Ω MAX @ VDS=1.8V)
• High Current (ID=0.95A)
• Logic Level Compatible
• Small, 1.5 x 2.0 x 0.4mm Ultra Low Height Profile TLM^™
MAXIMUM RATINGS: (TA=25°C)
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (Steady State)
Continuous Drain Current, t≤5.0s
Continuous Source Current (Body Diode)
Maximum Pulsed Drain Current, tp=10μs
Maximum Pulsed Source Current, tp=10μs
Power Dissipation (Note 1)
Operating and Storage Junction Temperature
Thermal Resistance (Note 1)
SYMBOL
VDS
VGS
ID
ID
IS
IDM
ISM
PD
TJ, Tstg
Θ_JA
20
8.0
860
950
360
4.0
4.0
1.6
-65 to +150
75
UNITS
V
V
mA
mA
mA
A
A
W
°C
°C/W
ELECTRICAL CHARACTERISTICS: (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
TYP
IGSSF, IGSSR
IDSS
BVDSS
VGS(th)
VSD
rDS(ON)
rDS(ON)
rDS(ON)
rDS(ON)
gFS
VGS=8.0V, VDS=0
VDS=20V, VGS=0
VGS=0, ID=250μA
VDS=VGS, ID=250μA
VGS=0, IS=360mA
VGS=4.5V, ID=0.95A
VGS=4.5V, ID=0.77A
VGS=2.5V, ID=0.67A
VGS=1.8V, ID=0.2A
VDS=10V, ID=810mA
1.0
5.0
20
24
0.45
0.76
85
85
130
190
2.0
Notes: (1) Mounted on a 4-layer JEDEC test board with one thermal vias connecting the
exposed thermal pad to the first buried plane. PCB was constructed as per
JEDEC standards JESD51-5 and JESD51-7.
MAX
50
500
1.0
0.9
150
142
200
240
UNITS
nA
nA
V
V
V
mΩ
mΩ
mΩ
mΩ
S
R1 (17-February 2010)