CTLDM8002A-M621H Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – SURFACE MOUNT TLM P-CHANNEL ENHANCEMENT-MODE SILICON MOSFET

CTLDM8002A-M621H
SURFACE MOUNT TLM^TM
P-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
Central^TM
Semiconductor Corp.
DESCRIPTION:
The CENTRAL SEMICONDUCTOR CTLDM8002A-M621H
is a very low profile (0.4mm) P-Channel enhancement-mode
MOSFET in a small, thermal efficient, 1.5mm x 2mm TLM™
package.
Top View
Bottom View
TLM621H CASE
MARKING CODE: CMA
FEATURES:
• Low RDS(on)
• Low VDS(on)
• Low Threshold Voltage
APPLICATIONS:
• Load/Power Switches
• Power Supply Converter
Circuits
• Fast Switching
• Logic Level Compatible
• Small, Very Low Profile, TLM™
• Battery Powered Portable
Equipment
MAXIMUM RATINGS (TA=25°C)
SYMBOL
UNITS
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
VDS
VDG
VGS
ID
50
V
50
V
20
V
280
mA
PRELIMINARY ^{Continuous Source Current (Body Diode)}
Maximum Pulsed Drain Current
Maximum Pulsed Source Current
Power Dissipation (Note 1)
Operating and Storage
Junction Temperature
Thermal Resistance (Note 1)
IS
IDM
ISM
PD
TJ,Tstg
Θ_JA
280
1.5
1.5
1.6
-65 to +150
75
ELECTRICAL CHARACTERISTICS (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
IGSSF
VGS=20V, VDS=0V
IGSSR
VGS=20V, VDS=0V
IDSS
VDS=50V, VGS=0V
IDSS
VDS=50V, VGS=0V, Tj=125°C
ID(ON)
VGS=10V, VDS=10V
500
BVDSS
VGS=0V, ID=10µA
50
MAX
100
100
1.0
500
mA
A
A
W
°C
°C/W
UNITS
nA
nA
µA
µA
mA
V
Notes: (1) Mounted on a 4-layer JEDEC test board with one thermal vias connecting the
exposed thermal pad to the first buried plane. PCB was constructed as per
JEDEC standards JESD51-5 and JESD51-7.
R0 (15-June 2006)