CTLDM7002A-M621H Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET

CTLDM7002A-M621H
SURFACE MOUNT
N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
w w w. c e n t r a l s e m i . c o m
DESCRIPTION:
The CENTRAL SEMICONDUCTOR CTLDM7002A-
M621H is a very low profile (0.4mm) Silicon N-Channel
Enhancement-mode MOSFET in a small, thermally
efficient, 1.5mm x 2mm TLM™ package.
MARKING CODE: CND
TLM621H CASE
• Device is Halogen Free by design
APPLICATIONS:
• Load/Power Switches
• Power Supply Converter Circuits
• Battery Powered Portable Equipment
FEATURES:
• Low rDS(ON)
• Low VDS(ON)
• Low Threshold Voltage
• Fast Switching
• Logic Level Compatible
• Small, Very Low Profile, TLM™
MAXIMUM RATINGS: (TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Continuous Source Current (Body Diode)
Maximum Pulsed Drain Current
Maximum Pulsed Source Current
Power Dissipation (Note 1)
Operating and Storage Junction Temperature
Thermal Resistance (Note 1)
SYMBOL
VDS
VDG
VGS
ID
IS
IDM
ISM
PD
TJ, Tstg
Θ_JA
60
60
40
280
280
1.5
1.5
1.6
-65 to +150
75
ELECTRICAL CHARACTERISTICS: (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
IGSSF, IGSSR VGS=20V, VDS=0
100
IDSS
VDS=60V, VGS=0
1.0
IDSS
VDS=60V, VGS=0, TJ=125°C
500
ID(ON)
VGS=10V, VDS=10V
500
BVDSS
VGS=0, ID=10μA
60
VGS(th)
VDS=VGS, ID=250μA
1.0
2.5
VDS(ON)
VGS=10V, ID=500mA
1.0
VDS(ON)
VGS=5.0V, ID=50mA
0.15
VSD
VGS=0, IS=400mA
1.2
Notes: (1) Mounted on a 4-layer JEDEC test board with one thermal vias connecting the
exposed thermal pad to the first buried plane. PCB was constructed as per
JEDEC standards JESD51-5 and JESD51-7.
UNITS
V
V
V
mA
mA
A
A
W
°C
°C/W
UNITS
nA
μA
μA
mA
V
V
V
V
V
R2 (17-February 2010)