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| CP709_06 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Power Transistor PNP - Low Saturation Transistor Chip | |||
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PROCESS CP709
Power Transistor
PNP - Low Saturation Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
41.3 x 41.3 MILS
9.0 MILS
9.5 x 9.2 MILS
12.8 x 10.2 MILS
Al - 30,000Ã
Au - 18,000Ã
GROSS DIE PER 4 INCH WAFER
6,670
PRINCIPAL DEVICE TYPES
CMPT7090L
CXT7090L
CZT7090L
CMXT7090L
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R3 (23- August 2006)
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