CP707_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Small Signal Transistor PNP - Darlington Transistor Chip

PROCESS CP707
Small Signal Transistor
PNP - Darlington Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
27 x 27 MILS
9.0 MILS
5.3 x 3.8 MILS
5.3 x 6.5 MILS
Al - 30,000Å
Au - 18,000Å
GROSS DIE PER 4 INCH WAFER
15,165
PRINCIPAL DEVICE TYPES
CMPTA63
CMPTA64
CXTA64
CZTA64
MPSA63
MPSA64
BACKSIDE COLLECTOR
w w w. c e n t r a l s e m i . c o m
R6 (22-March 2010)