CP705_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Small Signal Transistor PNP - High Current Transistor Chip

PROCESS CP705
Small Signal Transistor
PNP - High Current Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
31 x 31 MILS
9.0 MILS
5.9 x 11.8 MILS
6.5 x 13.8 MILS
Al - 30,000Å
Au - 18,000Å
GROSS DIE PER 4 INCH WAFER
11,212
PRINCIPAL DEVICE TYPES
2N4033
CMPT4033
CXT4033
CZT4033
w w w. c e n t r a l s e m i . c o m
R4 (22-March 2010)