CP701 Datasheet, PDF (1/1 Pages) Central Semiconductor Corp – Small Signal Transistors PNP - High Voltage Transistor Chip

PROCESS CP701
Small Signal Transistors
PNP - High Voltage Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
26 x 26 MILS
9.0 MILS
6.1 x 4.9 MILS
5.2 x 5.2 MILS
Al - 30,000Å
Au - 18,000Å
GROSS DIE PER 4 INCH WAFER
16,880
PRINCIPAL DEVICE TYPES
CMPT6520
CMPTA92
CXTA92
CZTA92
MPSA92
BACKSIDE COLLECTOR
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: [phone]
Fax: [phone]
www.centralsemi.com
R1 (27- November 2001)