CP555_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Small Signal Transistor PNP - Saturated Switch Transistor Chip

PROCESS CP555
Small Signal Transistor
PNP - Saturated Switch Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
EPITAXIAL PLANAR
15 x 10 MILS
8.0 MILS
3.6 x 2.4 MILS
3.6 x 2.4 MILS
Al - 20,000Å
Au - 15,000Å
GEOMETRY
BACKSIDE COLLECTOR
GROSS DIE PER 4 INCH WAFER
76,000
PRINCIPAL DEVICE TYPES
CMPT3640
CMPT4209
2N4209
w w w. c e n t r a l s e m i . c o m
R4 (22-March 2010)