CP547 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Power Transistor PNP - Darlington Chip

PROCESS CP547
Power Transistor
PNP - Darlington Chip
Central^TM
Semiconductor Corp.
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL BASE
195 X 195 MILS
12 MILS
29 X 29 MILS
61 X 35 MILS
AI - 30,000Å
Ti/Ni/Au - 6,000Å
GROSS DIE PER 5 INCH WAFER
290
PRINCIPAL DEVICE TYPES
MJ11011 2N6285
MJ11013 2N6286
MJ11015 2N6287
BACKSIDE COLLECTOR
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: [phone]
Fax: [phone]
www.centralsemi.com
R3 (1-August 2002)