CP319_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Power Transistor NPN - Silicon Power Transistor Chip

PROCESS CP319
Power Transistor
NPN - Silicon Power Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
87 x 87 MILS
9.0 MILS
24 x 15 MILS
38 x 16 MILS
Al - 30,000Å
Ti/Ni/Ag - 11,000Å
GROSS DIE PER 4 INCH WAFER
1,462
PRINCIPAL DEVICE TYPES
CZTA44HC
TIP47
TIP48
TIP50
BACKSIDE COLLECTOR
w w w. c e n t r a l s e m i . c o m
R3 (22-March 2010)