CP310_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Small Signal Transistor NPN - High Voltage Transistor Chip

PROCESS CP310
Small Signal Transistor
NPN - High Voltage Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
26 x 26 MILS
9.0 MILS
6.1 x 4.9 MILS
5.2 x 5.2 MILS
Al - 30,000Å
Au - 18,000Å
GROSS DIE PER 5 INCH WAFER
25,214
PRINCIPAL DEVICE TYPES
2N3439
2N3440
CMPTA42
CMPTA44
CMPT6517
CXTA44
CZTA42
CZTA44
MPSA42
MPSA44
w w w. c e n t r a l s e m i . c o m
R4 (22-March 2010)