CP309_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Power Transistor NPN - Low Saturation Transistor Chip

PROCESS CP309
Power Transistor
NPN - Low Saturation Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
EPITAXIAL PLANAR
41.3 x 41.3 MILS
9.0 MILS
9.4 x 9.2 MILS
12.8 x 10.2 MILS
Al - 30,000Å
Ag - 12,000Å
GEOMETRY
E
GROSS DIE PER 4 INCH WAFER
6,285
PRINCIPAL DEVICE TYPES
CMPT3090L
CXT3090L
B
CZT3090L
CMXT3090L
BACKSIDE COLLECTOR
R1
w w w. c e n t r a l s e m i . c o m
R4 (22-March 2010)