CP305-2N3019 Datasheet, PDF (1/3 Pages) Central Semiconductor Corp – NPN - High Current Transistor Die

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CP305-2N3019
NPN - High Current Transistor Die
The CP305-2N3019 is a silicon NPN transistor designed for high current, general purpose
applications.
MECHANICAL SPECIFICATIONS:
Die Size
31 x 31 MILS
Die Thickness
9.0 MILS
Base Bonding Pad Size
5.9 x 11.8 MILS
E
B
Emitter Bonding Pad Size 6.5 x 13.8 MILS
Top Side Metalization
Al – 30,000Å
Back Side Metalization
Au – 18,000Å
Scribe Alley Width
1.96 MILS
Wafer Diameter
4 INCHES
Gross Die Per Wafer
11,212
MAXIMUM RATINGS: (TA=25°C)
Collector-Base Voltage
Collector-Emitter Voltage
Emitter-Base Voltage
Continuous Collector Current
Operating and Storage Junction Temperature
ELECTRICAL CHARACTERISTICS: (TA=25°C)
SYMBOL TEST CONDITIONS
ICBO
VCB=90V
IEBO
VEB=5.0V
BVCBO
IC=100μA
BVCEO
IC=30mA
BVEBO
IE=100μA
VCE(SAT) IC=150mA, IB=15mA
VCE(SAT) IC=500mA, IB=50mA
VBE(SAT) IC=150mA, IB=15mA
hFE
VCE=10V, IC=100μA
hFE
VCE=10V, IC=10mA
hFE
VCE=10V, IC=150mA
hFE
VCE=10V, IC=500mA
hFE
VCE=10V, IC=1.0A
fT
VCE=10V, IC=50mA, f=20MHz
Cob
VCB=10V, IE=0, f=1.0MHz
Cib
VEB=0.5V, IC=0, f=1.0MHz
SYMBOL
VCBO
VCEO
VEBO
IC
TJ, Tstg
MIN
140
80
7.0
50
90
100
50
15
100
140
80
7.0
1.0
-65 to +150
MAX
10
10
0.2
0.5
1.1
300
12
60
UNITS
V
V
V
A
°C
UNITS
nA
nA
V
V
V
V
V
V
MHz
pF
pF
PACKING OPTIONS:
• CP305-2N3019-CT: Singulated die in waffle pack; 400 die per tray.
• CP305-2N3019-WN: Full wafer, unsawn, 100% tested with reject die inked.
• CP305-2N3019-WR: Full wafer, sawn and mounted on plastic ring, 100% tested with reject die inked.
R0 (12-March 2015)