CP230_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Power Transistor NPN - Silicon Darlington Transistor Chip

PROCESS CP230
Power Transistor
NPN - Silicon Darlington Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL BASE
80 x 80 MILS
8.0 MILS
18 x 27 MILS
34 x 34 MILS
Al - 30,000Å
Ti/Pd/Ag - 20,000Å
GROSS DIE PER 4 INCH WAFER
1,445
PRINCIPAL DEVICE TYPES
CZT122
CJD122
w w w. c e n t r a l s e m i . c o m
R2 (22-March 2010)