CP230 Datasheet, PDF (1/1 Pages) Central Semiconductor Corp – Power Transistors NPN - Silicon Darlington Transistor Chip

PROCESS CP230
Power Transistors
NPN - Silicon Darlington Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL BASE
80 X 80 MILS
8 MILS
18 X 27 MILS
34 X 34 MILS
Al - 30,000Å
Ti/Pd/Ag (20,000Å)
GROSS DIE PER 4 INCH WAFER
1,445
PRINCIPAL DEVICE TYPES
CZT122
CJD122
BACKSIDE COLLECTOR
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R0 (9 -May 2005)