CP208_10 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Power Transistor NPN - Amp/Switch Transistor Chip

PROCESS CP208
Power Transistor
NPN - Amp/Switch Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
66 x 66 MILS
12.5 ± 1.0 MILS
12 x 24 MILS
11 x 14 MILS
Al - 50,000Å
Cr/Ni/Ag - 16,000Å
GROSS DIE PER 4 INCH WAFER
2,630
PRINCIPAL DEVICE TYPES
CJD31C
MJE182
TIP31C
BACKSIDE COLLECTOR
w w w. c e n t r a l s e m i . c o m
R4 (22-March 2010)