CP188V Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – NPN - Low Noise Amplifier Transistor Chip

PROCESS CP188V
Small Signal Transistor
NPN - Low Noise Amplifier Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
14.6 x 14.6 MILS
7.1 MILS
3.9 x 3.9 MILS
5.5 x 5.5 MILS
Al - 30,000Å
Au-As - 18,000Å
GROSS DIE PER 4 INCH WAFER
54,599
PRINCIPAL DEVICE TYPES
CMPT2484
CMPT5088
CMPT5089
CMPT6428
CMPT6429
2N2484
BACKSIDE COLLECTOR R1
w w w. c e n t r a l s e m i . c o m
R0 (31-March 2010)