CP117 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – Power Transistor NPN - Darlington Chip

PROCESS CP117
Power Transistor
NPN - Darlington Chip
Central^TM
Semiconductor Corp.
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL BASE
111 X 111 MILS
10 MILS
20 X 30 MILS
20 X 26 MILS
Al - 30,000Å
Au/Cr/Ni/Au - Ni-6,000Å, Au-6,000Å
GROSS DIE PER 5 INCH WAFER
910
PRINCIPAL DEVICE TYPES
2N6043
2N6044
2N6045
2N6301
BACKSIDE COLLECTOR
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: [phone]
Fax: [phone]
www.centralsemi.com
R6 (1 -August 2002)