CMLDM7003G Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – SURFACE MOUNT PICOminiTM DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET

CMLDM7003
CMLDM7003G*
CMLDM7003J
SURFACE MOUNT PICOmini^TM
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
Central^TM
Semiconductor Corp.
DESCRIPTION:
These CENTRAL SEMICONDUCTOR devices are dual
Enhancement-mode N-Channel Field Effect Transistors,
manufactured by the N-Channel DMOS Process, designed
for high speed pulsed amplifier and driver applications. The
CMLDM7003 utilizes the USA pinout configuration, while
the CMLDM7003J utilizes the Japanese pinout
configuration. These devices offer low rDS _(ON) and ESD
protection up to 2kV.
SOT-563 CASE
* Device is Halogen Free by design
MARKING CODES: CMLDM7003:
CMLDM7003G*:
CMLDM7003J:
C30
C3G
C3J
MAXIMUM RATINGS: (TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Maximum Pulsed Drain Current
Power Dissipation (Note 1)
Power Dissipation (Note 2)
Power Dissipation (Note 3)
Operating and Storage Junction Temperature
Thermal Resistance
SYMBOL
VDS
VDG
VGS
ID
IDM
PD
PD
PD
TJ, Tstg
Θ_JA
50
50
12
280
1.5
350
300
150
-65 to +150
357
UNITS
V
V
V
mA
A
mW
mW
mW
°C
°C/W
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN TYP
MAX
IGSSF, IGSSR VGS=5.0V
100
IGSSF, IGSSR VGS=10V
2.0
IGSSF, IGSSR VGS=12V
2.0
IDSS
VDS=50V, VGS=0V
50
BVDSS
VGS=0V, ID=10μA
50
VGS(th)
VDS=VGS, ID=250μA
0.49
1.0
VSD
VGS=0V, IS=115mA
1.4
rDS(ON)
VGS=1.8V, ID=50mA
1.6
3.0
rDS(ON)
VGS=2.5V, ID=50mA
1.3
2.5
rDS(ON)
gFS
VGS=5.0V, ID=50mA
VDS=10V, ID=200mA
1.1
2.0
200
Crss
VDS=25V, VGS=0, f=1.0MHz
5.0
Ciss
VDS=25V, VGS=0, f=1.0MHz
50
Coss
VDS=25V, VGS=0, f=1.0MHz
25
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0 mm²
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0 mm²
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4 mm²
UNITS
nA
μA
μA
nA
V
V
V
Ω
Ω
Ω
mS
pF
pF
pF
R5 (8-January 2009)