CMLDM7003 Datasheet, PDF (1/2 Pages) Central Semiconductor Corp – SURFACE MOUNT PICOmini DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET

CMLDM7003
CMLDM7003J
SURFACE MOUNT PICOmini^TM
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
SOT-563 CASE
Central^TM
Semiconductor Corp.
DESCRIPTION:
The CENTRAL SEMICONDUCTOR CMLDM7003 and
CMLDM7003J are Enhancement-mode N-Channel Field
Effect Transistors, manufactured by the N-Channel
DMOS Process, designed for high speed pulsed amplifier
and driver applications. The CMLDM7003 utilizes the
USA pinout configuration, while the CMLDM7003J utilizes
the Japanese pinout configuration. These special Dual
Transistor devices offer low drain-source on state
resistance (rDS(ON)).
MARKING CODE: CMLDM7003: C30
CMLDM7003J: C3J
MAXIMUM RATINGS (TA=25°C)
SYMBOL
PRELIMINARY ^{Drain-Source Voltage}
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Maximum Pulsed Drain Current
Power Dissipation
Power Dissipation
Power Dissipation
Operating and Storage
Junction Temperature
Thermal Resistance
VDS
VDG
VGS
ID
IDM
PD
PD
PD
TJ,Tstg
Θ_JA
50
50
40
300
1.2
350
300
150
-65 to +150
357
ELECTRICAL CHARACTERISTICS PER TRANSISTOR
SYMBOL
TEST CONDITIONS
IGSSF, IGSSR
IGSSF, IGSSR
IGSSF, IGSSR
IDSS
VGS=5V
VGS=10V
VGS=12V
VDS=50V, VGS=0V
(TA=25°C unless otherwise noted)
MIN TYP
MAX
50
500
1.0
50
BVDSS
VGS=0V, ID=10µA
50
VGS(th)
VDS=VGS, ID=250µA
0.5
1.2
rDS(ON)
VGS=1.8V, ID=50mA
1.6
2.3
rDS(ON)
rDS(ON)
gFS
Crss
VGS=2.5V, ID=50mA
VGS=5.0V, ID=50mA
VDS=10V, ID=200mA
VDS=25V, VGS=0, f=1.0MHz
1.3
1.1
200
1.9
1.5
TBD
Ciss
Coss
VSD
VDS=25V, VGS=0, f=1.0MHz
VDS=25V, VGS=0, f=1.0MHz
VGS=0V, IS=115mA
TBD
TBD
1.4
UNITS
V
V
V
mA
A
mW (Note 1)
mW (Note 2)
mW (Note 3)
°C
°C/W
UNITS
nA
nA
µA
nA
V
V
Ω
Ω
Ω
mmhos
pF
pF
pF
V
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0 mm²
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0 mm²
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4 mm²
R0 (26-June 2006)