NE5520379A Datasheet, PDF (1/9 Pages) California Eastern Labs – NECs 3.2V, 3W, L/S BAND MEDIUM POWER SILICON LD-MOSFET

NEC'S 3.2 V, 3 W, L/S BAND
MEDIUM POWER SILICON LD-MOSFET
NE5520379A
FEATURES
OUTLINE DIMENSIONS (Units in mm)
• LOW COST PLASTIC SURFACE MOUNT PACKAGE
• HIGH OUTPUT POWER: +35.5 dBm TYP
• HIGH LINEAR GAIN: 16 dB TYP @ 915 MHz
• HIGH POWER ADDED EFFICIENCY: 65% TYP @
VDS = 3.2 V, f = 915 MHz
• SINGLE SUPPLY: 2.8 to 6.0 V
• CLASS AB OPERATION
• SURFACE MOUNT PACKAGE: 5.7x5.7x1.1 mm MAX
PACKAGE OUTLINE 79A
(Bottom View)
4.2 MAX.
1.5±0.2
Source
Source
Gate
Drain
Gate
Drain
0.4±0.15
0.8 MAX.
DESCRIPTION
5.7 MAX.
3.6±0.2
NEC's NE5520379A is an N-Channel silicon power MOSFET
specially designed as the transmission power amplifier for
3.2 V GSM900 handsets. Die are manufactured using NEC's
NEWMOS technology (NEC's 0.6 μm WSi gate lateral MOS-
FET) and housed in a surface mount package. This device
can deliver 35.5 dBm output power at 915 MHz and 3.2 V, or
34.6 dBm output power at 2.8 V by varying the gate voltage
as a power control function.
ELECTRICAL CHARACTERISTICS (TA = 25°C)
APPLICATIONS
• DIGITAL CELLULAR PHONES:
3.2 V GSM900/DCS 1800 Dual Band Handsets
• OTHERS:
Two-Way Pagers
Retail Business Radio
Special Mobile Radio
Short Range Wireless
SYMBOLS
POUT
GL
ηD
ηADD
ID
POUT
GL
ID
ηD
ηADD
IGSS
IDSS
VTH
gm
BVDSS
RTH
PART NUMBER
PACKAGE OUTLINE
CHARACTERISTICS
Output Power
Linear Gain (at PIN = +10 dBm)
Drain Efficiency
Power Added Efficiency
Operating Drain Current
Output Power
Linear Gain (at PIN = +10 dBm)
Operating Drain Current
Drain Efficiency
Power Added Efficiency
Gate-to-Source Leakage Current
Drain-to-Source Leakage Current
Gate Threshold Voltage
Transconductance
Drain-to-Source Breakdown Voltage
Thermal Resistance
UNITS
dBm
dB
%
%
A
dBm
dB
mA
%
%
nA
nA
V
S
V
°C/W
NE5520379A
79A
MIN
TYP
MAX
35.5
16.0
68
65
1.0
31.0
33.0
8.5
750
29
38
35
100
100
1.0
1.35
2.0
2.5
15
20
5
TEST CONDITIONS
f = 915 MHz, VDS = 3.2 V,
VGS = 2.5 V(RF OFF)
(NOTE 1)
f = 1785 MHz, VDS = 3.2 V,
VGS = 2.5 V
(NOTE 1)
VGS = 6.0 V
VDS = 8.5 V
VDS = 3.5 V, IDS = 1 mA
VDS = 3.5 V, IDS1 = 0.8 A, IDS2 = 1.0 A
IDSS = 10 µA
Channel-to-Case
Note:
1. DC performance is tested 100%. Several samples per wafer are tested for RF performance. Wafer rejection criteria for standard devices is 1
reject for several samples.
California Eastern Laboratories