NE33200 Datasheet, PDF (1/7 Pages) California Eastern Labs – SUPER LOW NOISE HJ FET

SUPER LOW NOISE HJ FET ^NE33200
FEATURES
• VERY LOW NOISE FIGURE:
0.75 dB typical at 12 GHz
• HIGH ASSOCIATED GAIN:
10.5 dB Typical at 12 GHz
• GATE LENGTH: 0.3 µm
• GATE WIDTH: 280 µm
DESCRIPTION
The NE33200 is a Hetero-Junction FET chip that utilizes the
junction between Si-doped AlGaAs and undoped InGaAs to
create a two-dimensional electron gas layer with very high
electron mobility. Its excellent low noise figure and high
associated gain make it suitable for commercial and industrial
applications.
NEC's stringent quality assurance and test procedures as-
sure the highest reliability and performance.
NOISE FIGURE & ASSOCIATED
GAIN vs. FREQUENCY
VDS = 2 V, IDS = 10 mA
4
24
3.5
21
Ga
3
18
2.5
15
2
12
1.5
9
1
0.5
0
1
NF
10
Frequency, f (GHz)
6
3
0
30
ELECTRICAL CHARACTERISTICS (TA = 25°C)
PART NUMBER
PACKAGE OUTLINE
NE33200
00 (Chip)
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
NFOPT¹
GA¹
Noise Figure, VDS = 2 V, ID = 10 mA,
f = 4 GHz
f = 12 GHz
Associated Gain, VDS = 2 V, ID = 10 mA,
f = 4 GHz
f = 12 GHz
dB
0.35
dB
0.75
1.0
dB
15.0
dB
9.5
10.5
P1dB
Output Power at 1 dB Gain Compression Point, f = 12 GHz
VDS = 2 V, IDS = 10 mA
dBm
11.2
VDS = 2 V, IDS = 20 mA
dBm
12.0
G1dB
Gain at P1dB, f = 12 GHz
VDS = 2 V, IDS = 10 mA
VDS = 2 V, IDS = 20 mA
dB
11.8
dB
12.8
IDSS
Saturated Drain Current, VDS = 2 V, VGS = 0 V
mA
15
40
80
VP
Pinch-off Voltage, VDS = 2 V, ID = 100 µA
V
-2.0
-0.8
-0.2
gm
IGSO
RTH(CH-C)2
Transconductance, VDS = 2 V, ID = 10 mA
Gate to Source Leakage Current, VGS = -5 V
Thermal Resistance (Channel to Case)
mS
45
µA
°C/W
70
0.5
10
240
Notes:
1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects for
10 samples.
2. Chip mounted on infinite heat sink.
California Eastern Laboratories