NE321000_01 Datasheet, PDF (1/6 Pages) California Eastern Labs – ULTRA LOW NOISE PSEUDOMORPHIC HJ FET

ULTRA LOW NOISE
PSEUDOMORPHIC HJ FET
NE321000
FEATURES
• SUPER LOW NOISE FIGURE:
0.35 dB Typ at f = 12 GHz
• HIGH ASSOCIATED GAIN:
13.0 dB Typ at f = 12 GHz
• GATE LENGTH: ≤0.2 µm
• GATE WIDTH: 160 µm
DESCRIPTION
NEC's NE321000 is a Hetero-Junction FET chip that utilizes
the junction between Si-doped AlGaAs and undoped InGaAs
to create high electron mobility. Its excellent low noise figure
and high associated gain make it suitable for commercial,
industrial and space applications.
NEC's stringent quality assurance and test procedures assure
the highest reliability and performance.
NOISE FIGURE & ASSOCIATED GAIN vs.
DRAIN CURRENT
VDS = 2 V
15
f = 12 GHz
GA
14
13
2.0
12
1.5
11
1.0
0.5
NF
0
10
20
30
Drain Current, ID (mA)
ELECTRICAL CHARACTERISTICS (TA = 25°C)
PART NUMBER
PACKAGE OUTLINE
NE321000
CHIP
SYMBOLS
NF
GA1
PARAMETERS AND CONDITIONS
Noise Figure, VDS = 2 V, ID = 10 mA, f = 12 GHz
Associated Gain, VDS = 2 V, ID = 10 mA, f = 12 GHz
UNITS
MIN
TYP
MAX
dB
0.35
0.45
dB
12.0
13.5
IDSS
Saturated Drain Current, VDS = 2 V, VGS = 0 V
mA
15
40
70
VP
gM
IGSO
Pinch-off Voltage, VDS = 2 V, ID = 100 µA
Transconductance, VDS = 2 V, ID = 10 µA
Gate to Source Leakage Current, VGS = -3 V
V
-0.2
-0.7
-2.0
mS
40
55
µA
0.5
10
Note:
1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects per
10 samples.
California Eastern Laboratories