CAT3636_08 Datasheet, PDF (9/16 Pages) Catalyst Semiconductor – 6-Channel Quad-ModeTM Fractional LED Driver in TQFN3x3

LED Current Setting
The current in each of the six LED channels is
programmed through the 1-wire EN/SET digital control
input. By pulsing this signal according to a specific
protocol, a set of internal registers can be addressed
and written into allowing to configure each bank of
LEDs with the desired current. There are six registers:
the first five are 4 bits long and the sixth is 1 bit long.
The registers are programmed by first selecting the
register address and then programming data into that
register.
An internal counter records the number of falling
edges to identify the address and data. The address is
serially programmed adhering to low and high
duration time delays. One down pulse corresponds to
register 1 being selected. Two down pulses
correspond to register 2 being selected and so on up
to register 6. T_LO and T_HI must be within 200ns to
100μs. Anything below 200ns may be ignored.
Once the final rising edge of the address pointer is
programmed, the user must wait 500μs to 1000μs
before programming the first data pulse falling edge. If
the falling edge of the data is not received within
1000μs, the device will revert back to waiting for an
address.
CAT3636
Data in a register is reset once it is selected by the
address pointer. If a register is selected but no data is
programmed, then the register value is reset back to
its initial default value with all data bits to 0.
Once the final rising edge of the data pulses is
programmed, the user must wait 1.5ms before
programming another address. If programming fails or
is interrupted, the user must wait T_RESETDELAY 2ms from
the last rising edge before reprogramming can
commence.
Upon power-up, the device automatically starts
looking for an address. The device requires a
minimum 10μs delay (T_SETUP) to ensure the
initialization of the internal logic at power-up. After this
time delay, the device registers may be programmed
adhering to the timing constraints shown in Figure 1. If
no falling edge is detected within 100μs of power-up,
then the user must wait 2ms before trying to program
the device again.
To power-down the device and turn-off all current
sources, the EN/SET input should be kept low for a
duration T_OFF of 1.5ms or more. The driver typically
powers-down with a delay of about 1ms. All register
data are lost.
Figure 3. EN/SET One Wire Addressable Timing Diagram
© Catalyst Semiconductor, Inc.
9
Characteristics subject to change without notice
Doc. No. MD-5020 Rev. D