CAT24C256 Datasheet, PDF (9/14 Pages) Catalyst Semiconductor – 256-Kb I2C CMOS Serial EEPROM

Figure 8. Immediate Address Read Timing
S
T
S
BUS ACTIVITY: ^A
SLAVE
T
MASTER ^R ADDRESS
O
T
P
SDA LINE S
P
A
N
C
DATA
O
K
A
C
K
SCL
8
9
SDA
8th Bit
DATA OUT
NO ACK
STOP
CAT24C256
Figure 9. Selective Read Timing
S
T
BUS ACTIVITY:
MASTER
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
S
T
A
R
T
SLAVE
ADDRESS
S
T
DATA
O
P
SDA LINE S
*
S
P
A
A
A
C
C
C
* ^{= Don't Care Bit}
K
K
K
A
N
C
O
K
A
C
K
Figure 10. Sequential Read Timing
BUS ACTIVITY: SLAVE
MASTER ADDRESS
SDA LINE
A
C
K
DATA n
DATA n+1
DATA n+2
A
A
A
C
C
C
K
K
K
S
T
DATA n+x
O
P
P
N
O
A
C
K
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

Doc No. 1104, Rev. D