CAT1640 Datasheet, PDF (9/18 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial 64K CMOS EEPROM

Advance Information
CAT1640, CAT1641
ACKNOWLEDGE
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT1640/41 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT1640/41 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1640/41 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8-bit
address bytes that are to be written into the address
pointers of the device. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the addressed memory location. The CAT1640/
41 acknowledges once more and the Master generates
the STOP condition. At this time, the device begins an
internal programming cycle to non-volatile memory. While
the cycle is in progress, the device will not respond to any
request from the Master device.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
1
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 7. Slave Address Bits
ACKNOWLEDGE
Default Co_Cn_Af_Tiguration
1 0 1 0 A2 A1 A0 R/W
9
Doc No. 25082, Rev. 00