CAT24WC32 Datasheet, PDF (8/10 Pages) Catalyst Semiconductor – 32K/64K-Bit I2C Serial CMOS E2PROM

CAT24WC32/64
Figure 9. Selective Read Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
SDA LINE S
XXX *
A
A
C
C
K
K
* = Don't care bit for 24WC32
X= Don't care bit
S
T
A _SLAVE
R _ADDRESS
T
S
A
A
C
C
K
K
DATA
S
T
O
P
P
N
O
A
C
K
24WC32/64 F11
Figure 10. Sequential Read Timing
BUS ACTIVITY: SLAVE
MASTER ADDRESS
SDA LINE
A
C
K
DATA n
DATA n+1
DATA n+2
A
A
A
C
C
C
K
K
K
DATA n+x
S
T
O
P
P
N
O
A
C
K
5020 FHD F12
Doc. No. 1039, Rev. F
8