CAT523_07 Datasheet, PDF (7/15 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometer (DPP™) with 256 Taps and Microwire Interface

CAT523
No clock is necessary upon system power-up. The
CAT523’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using
the external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking
data into the control registers. Standard CMOS and
TTL logic families work well in this regard and it is
recommended that any mechanical switches used for
breadboarding or device evaluation purposes be
debounced by a flip-flop or other suitable debouncing
circuit.
RDY/¯B¯S¯Y¯ will remain high following the program
command indicating a failure to record the desired
data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT523, LSB first, via
the Data Out (DO) pin following the reception of a
start bit and two address bits by the Data Input (DI).
DO becomes active whenever CS goes high and
resumes its high impedance Tri-State mode when CS
returns low. Tri-Stating the DO pin allows several
523s to share a single serial data line and simplifies
interfacing multiple 523s to a microprocessor.
V_REF
V_REF, the voltage applied between pins V_REFH & V_REFL,
sets the DPP’s Zero to Full Scale output range where
V_REFL = Zero and V_REFH = Full Scale. V_REF can span
the full power supply range or just a fraction of it. In
typical applications V_REFH & V_REFL are connected
across the power supply rails. When using less than
the full supply voltage V_REFH is restricted to voltages
between V_DD and V_DD/2 and V_REFL to voltages between
GND and V_DD/2.
READY/B¯¯U¯S¯Y¯
When saving data to non-volatile memory, the
Ready/Busy output (RDY/¯B¯S¯Y¯) signals the start and
duration of the non-volatile erase/write cycle. Upon
receiving a command to store data (PROG goes high)
RDY/¯B¯S¯Y¯ goes low and remains low until the
programming cycle is complete. During this time the
CAT523 will ignore any data appearing at DI and no
data will be output on DO.
RDY/¯B¯S¯Y¯ is internally ANDed with a low voltage
detector circuit monitoring VDD. If VDD is below the
minimum value required for non-volatile programming,
Figure 1. Writing to Memory
WRITING TO MEMORY
Programming the CAT523’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start
bitfollowed by a two bit DPP address and eight data
bits are clocked into the DPP control register via the
DI pin. Data enters on the clock’s rising edge. The
DPP output changes to its new setting on the clock
cycle following D7, the last data bit.
Programming is achieved by bringing PROG high
sometime after the start bit and at least 150 ns prior to
the rising edge of the clock cycle immediately
following the D7 bit. Two clock cycles after the D7 bit
the DAC control register will be ready to receive the
next set of address and data bits. The clock must be
kept running throughout the programming cycle.
Internal control circuitry takes care of ramping the
programming voltage for data transfer to the non-
volatile memory cells. The CAT523’s non-volatile
memory cells will endure over 100,000 write cycles
and will retain data for a minimum of 100 years
without being refreshed.
to 1 2 3 4 5 6 7 8 9 10
11 12
N N+1 N+2
CS
NEW DPP DATA
DI
1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
DO
D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NON-VOL ATILE
NEW
DPP VALUE
VOLATILE
NEW
DPP VALUE
NON-VOL ATILE
© Catalyst Semiconductor, Inc.
7
Characteristics subject to change without notice
Doc. No. MD-2005 Rev. G