CAT5221 Datasheet, PDF (7/16 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

CAT5221
WRITE OPERATIONS
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the
requested operation of CAT5221. The instruction byte
consist of a four-bit opcode followed by two register
selection bits and two pot selection bits. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the selected register.
The CAT5221 acknowledges once more and the Master
generates the STOP condition, at which time if a non-
volatile data register is being selected, the device begins
an internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will not
respond to any request from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5221 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address. If the
CAT5221 is still busy with the write operation, no ACK
will be returned. If the CAT5221 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
Figure 5. Slave Address Bits
CAT5221 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
S
T ^{SLAVE/DPP INSTRUCTION}
S
BUS ACTIVITY: ^{A ADDRESS}
BYTE
T
MASTER ^R
T
Fixed
Variable
op code
DR WCR DATA ^{Pot/WCR Data Register}
Address Address
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
7
Document No. 2113, Rev. I