CAT28C17A Datasheet, PDF (7/8 Pages) Catalyst Semiconductor – 16K-Bit CMOS PARALLEL E2PROM

CAT28C17A
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
DATA Polling
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O7 (I/O0–I/O6 are indeter-
minate) until the programming cycle is complete. Upon
completion of the self-timed byte write cycle, all I/O’s will
output true data during a read cycle.
Figure 5. Byte Write Cycle [CE Controlled]
tWC
ADDRESS
tAS
tAH
tDL
tCW
CE
tOEH
OE
tOES
tCS
tCH
WE
RDY/BUSY
DATA OUT
tDB
HIGH-Z
DATA IN
Figure 6. DATA Polling
ADDRESS
DATA VALID
tDS
tDH
5091 FHD F07
CE
WE
OE
I/O7
tOEH
DIN = X
tOE
tWC
DOUT = X
tOES
DOUT = X
28C17A F08
7
Doc. No. 25034-00 2/98