CAT25CXXX Datasheet, PDF (7/12 Pages) Catalyst Semiconductor – Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer

Advanced
CAT25CXXX
DEVICE OPERATION FOR THE MEMORY
FUNCTION
Write Enable and Disable
The CAT25CXXX contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25CXXX, followed
by the 16-bit address for 25C08X/16X/32X (only 10-bit
addresses are used for 25C08X, 11-bit addresses are
used for 25C16X, and 12-bit addresses are used for
25C32X. The rest of the bits are don't care bits) and 8-
bit address for 25C02X/04X (for the 25C04X, bit 3 of the
read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000H allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by pulling the CS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be
read at any time even during a write cycle. Read
sequece is illustrated in Figure 4. Reading status register
is illustrated in Figure 5.
WRITE Sequence
The CAT25CXXX powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25CXXX. The device goes into
w rite enable state by pulling the CS low and then
clocking the WREN instruction into CAT25CXXX. The
CS must be brought high after the WREN instruction to
enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
Figure 2. WREN Instruction Timing
SK
CS
SI
00000 1 1 0
HIGH-Z
SO
9-101
Stock No. 21085-01 4/98