CAT25C01 Datasheet, PDF (7/10 Pages) Catalyst Semiconductor – 1K/2K/4K/8K/16K SPI Serial CMOS E2PROM

Advanced Information
CAT25C01/02/04/08/16
WRITE Sequence
The CAT25C01/02/04/08/16 powers up in a Write Dis-
able state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C01/02/04/08/16.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C01/02/04/08/16. The CS must be brought high
after the WREN instruction to enable writes to the
device. If the write operation is initiated immediately
after the WREN instruction without CS being brought
high, the data will not be written to the array because the
write enable latch will not have been properly set. Also,
for a successful write operation the address of the
memory location(s) to be programmed must be outside
the protected address field location selected by the
block protection level.
Figure 4. Read Instruction Timing
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
The rest of the bits are don't care bits) and 8-bit address
for 25C01/02/04 (for the 25C04, bit 3 of the read data
instruction contains address A8). Programming will start
after the CS is brought high. Figure 6 illustrates byte
write sequence.
CS
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
SI
0000001 1
BYTE ADDRESS*
SO
HIGH IMPEDANCE
*Please check the instruction set table for address
DATA OUT
7 6 5 432 1 0
MSB
Note: Dashed Line= mode (1, 1) – – – –
Figure 5. RDSR Instruction Timing
CS
SCK
SI
SO
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
0
0
0
0
0
HIGH IMPEDANCE
1
0
1
DATA OUT
7
6
5
4
3
2
10
MSB
Note: Dashed Line= mode (1, 1) – – – – –
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Doc. No. 25067-00 5/00