CAT24FC65 Datasheet, PDF (7/10 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection

CAT24FC65/66
READ OPERATIONS
The READ operation for the CAT24FC65/66 is initiated
in the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
The CAT24FC65/66’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=8,191),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24FC65/66
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After CAT24FC65/66 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/W bit set to one.
The CAT24FC65/66 then responds with its acknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC65/66 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC65/66 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24FC65/66 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24FC65/66 address
bits so that the entire memory array can be read during
one operation. If more than E (where E=8,191) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Figure 8. Immediate Address Read Timing
SCL
SDA
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
S
T
DATA
O
P
SDA LINE S
P
A
N
C
O
K
A
C
K
8
9
8TH BIT
DATA OUT
NO ACK
STOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. 1047, Rev. H