CAT24AC128 Datasheet, PDF (7/11 Pages) Catalyst Semiconductor – 128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins

CAT24AC128
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After CAT24AC128 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one. The
CAT24AC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24AC128 sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24AC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24AC128 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24AC128 address bits
so that the entire memory array can be read during one
operation. If more than E (where E=16383) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Figure 8. Current Address Read Timing
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SDA LINE S
SLAVE
ADDRESS
S
T
DATA
O
P
P
A
N
C
O
K
A
C
K
SCL
8
9
SDA
8TH BIT
DATA OUT
NO ACK
STOP
24AC128 F08
Figure 9. Random Address Read Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
S
T
A _SLAVE
R _ADDRESS
T
S
T
DATA
O
P
SDA LINE S
**
S
P
*=Don't Care Bit
A
A
A
C
C
C
K
K
K
A
N
C
O
K
A
C
K
7
Doc. No. 1028, Rev. I